Director - Silicon Product & Test Engineering

ABOUT US At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.   JOB SUMMARY Reporting to Senior Director of Post Silicon Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. You will lead teams passionate about identifying, reproducing, analyzing, and resolving complex silicon, firmware, and system-level issues during bring-up, characterization, and product readiness. This role combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering fields.   THE TEAM The Post-Silicon Debug and Validation team manages bring-up, fault diagnosis, and validation of Graphcore silicon and systems. Our team participates throughout the entire product lifecycle, supporting initial silicon bring-up, subsystem validation, system integration, and production readiness tasks. We coordinate closely with hardware, firmware, software, and systems teams to examine complex failures, develop debug strategies, and advance validation infrastructure.   RESPONSIBILITIES AND DUTIES * Lead post-silicon debugging and validation efforts for AI compute silicon and platform technologies * Contribute to debug and validation activities across multiple projects and achievements * Analyze and address intricate silicon, firmware, software, and system-level problems during bring-up and validation * Develop structured debug methodologies and failure analysis processes to improve issue resolution efficiency * Work in close partnership with architecture, RTL, firmware, software, and systems engineering groups to determine root causes and carry out corrective measures * Drive debug of CPU, memory, interconnect, and high-speed I/O subsystems under functional, stress, and workload conditions * Develop and improve automated debug, regression, and validation infrastructure using Python and related technologies * Analyze logs, traces, telemetry, and hardware data to isolate and characterize system failures and performance issues * Support development of validation tests, debug tooling, and custom diagnostics to improve coverage and observability * Define validation metrics, debug workflows, and reporting standards to ensure consistent and repeatable analysis * Communicate technical risks, status, and recommendations clearly to engineering leadership and cross-functional collaborators * Support silicon readiness reviews and contribute to product quality and release decisions * Contribute to continuous improvement of debug methodologies, validation infrastructure, and engineering workflows   CANDIDATE PROFILE ESSENTIAL: * Strong experience in bare metal environments * Strong understanding of SoC and platform architectures * Expertise in debug infrastructure and post-silicon debug methodologies * Strong programming skills in Python, C, or debug scripting languages such as CMM or equivalent experience * Highly motivated self-starter with a collaborative and team-oriented approach * Ability to collaborate across teams and programming languages to uncover root causes of deep and complex issues * Experience of the post-silicon validation process applied in digital ASIC environments * Strong Linux and Python experience * Outstanding communication skills and the ability to collaborate effectively to solve complex problems * Excellent problem-solving, analytical, and diagnostic skills * Deep knowledge of scan, DFT, JTAG, and trace infrastructure * Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies, and system-level debug techniques * Capability to operate autonomously on technically intricate debug and validation tasks spanning hardware, firmware, and software areas DESIRABLE * Understanding of DFT flows from insertion through post-silicon validation * Experience developing tooling for parsing and analyzing debug data, including scan dump parsing * Driver-level experience with one or more of the following technologies: PCIe, Ethernet, Memory technologies including LPDDR, DDR, and HBM, Peripheral interfaces such as I2C, I3C, and SPI * Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB, and STM or equivalent experience * Strong understanding of mixed-signal components like PLLs, high-speed PHYs, and IC control/communication protocols * Experience with Arm CPU architectures, system IP, and associated debug tooling * Experience with AMBA protocols * Understanding of ML applications and associated workloads * Experience in characterization, failure analysis, test development, statistical analysis, and customer support BENEFITS In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

About Graphcore  At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary  We are seeking a Director of Silicon Logical Design to lead and scale our Logical Design group within the Silicon department. This role is accountable for the overall strategy, technical direction, execution quality and team development for Graphcores microarchitecture and RTL design efforts.  The Director will be responsible for ensuring that our logical design methodologies, architectures and RTL implementations meet world class standards for performance, power, area, and schedule. This leader will partner closely with Architecture, Physical Design, Verification, DFT and Program Management teams to ensure successful, predictable silicon delivery aligned with Graphcores long term product roadmap.  The Team  The Logical Design team deliver the micro-architecture and RTL that realise our advanced chip architectures. As Director, you will guide this multi site team, strengthen cross functional collaboration, and drive the evolution of our design flows and capabilities.  Responsibilities and Duties  Leadership & Strategy  * Define and execute the strategic roadmap for Logical Design, ensuring alignment with Graphcores silicon and product strategy.  * Lead, grow and mentor a high performing RTL/micro architecture design organisation.  * Establish and implement best in class design methodologies, documentation standards and quality metrics.  * Drive continuous improvement across team structure, workflows, tooling, and design processes.    Technical Ownership  * Provide technical oversight of micro architecture specification and RTL development across all major blocks and subsystems.  * Guide architectural feasibility studies, contribute to architectural trade offs and micro architecture definition.  * Oversee the integration of third party IP, complex application specific blocks, and high performance custom designs.  * Ensure robust design sign off through high quality linting, synthesis, CDC/RDC, timing closure and coverage metrics.    Cross-Functional Collaboration  * Partner closely with Physical Design, Verification, DFT, Architecture and Program Management teams to ensure cohesive planning and execution.  * Foster strong communication across teams and global sites, ensuring alignment on priorities, risks and deliverables.  * Support silicon bring-up and debug efforts by providing expert guidance and deep understanding of RTL behaviour and architecture.    Execution & Delivery  * Own delivery of high quality, on schedule RTL for multiple parallel silicon programs.  * Establish scalable project planning and tracking practices, including resource planning and risk mitigation.  * Champion design automation and infrastructure improvements to accelerate productivity and improve design quality.  Essential Skills & Experience  * Degree in Computer Science, Electrical Engineering or a related field; advanced degree preferred.  * Extensive experience in digital logical design, micro-architecture and RTL development for large scale, high performance silicon projects.  * Proven success leading and developing technical teams in a semiconductor environment.  * Deep expertise in SystemVerilog or VHDL and familiarity with modern digital design flows.  * Strong ability to diagnose and resolve complex design issues, including via scripting/programming (Python, Tcl, etc.).  * Demonstrated excellence in cross functional leadership and communication across global teams.  * Strong organisational skills with ability to manage multiple priorities and drive execution in fast-paced environments.    Desirable Experience  * Processor or accelerator micro architecture.  * High-speed serial interfaces and complex, high bandwidth IP blocks.  * Arithmetic pipeline design and floating point datapaths.  * Advanced synthesis, timing analysis, power analysis, and logical equivalence checking.  * Design-for-test methodologies.  * Power integrity and silicon device level understanding.  * Experience with silicon bring-up and post-silicon validation.  * Program planning and multi-project execution leadership.